| 摘要 |
There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto-calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good circuit yield and is compatible with ASICs.
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