发明名称 INSTRUCTION RAM UPDATING CIRCUIT
摘要 <p>PURPOSE:To update an instruction RAM in the normal operation with a simple circuitry. CONSTITUTION:The circuit consists of a normal operation address register 12, updating address register 11, selector 13 selecting two types of address registers, and selector 14 switching the RAM output and the NOP code. In updating the RAM, the register 12 holds the former value and the value of the updating address register 11 is selected as the RAM address. As an instruction, the NOP code is selected instead of the RAM output.</p>
申请公布号 JPH05334197(A) 申请公布日期 1993.12.17
申请号 JP19920136553 申请日期 1992.05.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIGETA HIROMI
分类号 G06F1/24;G06F12/16;(IPC1-7):G06F12/16 主分类号 G06F1/24
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