| 摘要 |
PURPOSE:To shorten the time required for synchronism setlement and to miniaturize the memory scale for synchronous detection. CONSTITUTION:Data having the multiframe structure where a bit pattern inserted for frame synchronism is distributed at certain intervals is received, and reception data of a one-bit portion of one frame is held in a D flip flop circuit D1. Data of a one-bit portion of reception data of each frame written in one memory 5 is read out by address designation of an address control circuit 2 and is held in circuits D1 to D3. Four-bit data outputted from a data input/ output switching circuit 3 is taken into a synchronizing pattern detecting circuit 4 and is collated with a reference 4-bit synchronizing pattern, and a synchronous detection flag is outputted in the case of coincidence. Since the same memory 5 is used for the write of reception data and detection of the synchronizing pattern, the memory scale is minimized. |
