发明名称 FLASH MEMORY AND DATA PROCESSOR
摘要 <p>PURPOSE:To provide a flash memory whose memory cells can be made uniform in erasure characteristics even if memory cells which share a source have variance in source coupling capacity. CONSTITUTION:A couple of memory cells Q21 and Q31 share the source S1 of a flash memory cell; and only one memory cell is erased and then the other memory cell is erased. Namely, memory cells in an even-numbered row A2 are erased and memory cells in an odd--numbered row A3 are erased. While the even-numbered row is erased, an erasure preventing voltage is applied to the odd-numbered row and while the odd-numbered row is erased, the erasure preventing voltage is applied to the even-numbered row. Consequently, a difference in the capacity coupling ratio between the source between the couple of memory cells and a floating gate can be ignored.</p>
申请公布号 JPH05325573(A) 申请公布日期 1993.12.10
申请号 JP19930018095 申请日期 1993.01.08
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 SHIBA KAZUYOSHI;TERASAWA MASAAKI
分类号 G11C17/00;G11C16/02;G11C16/04;G11C16/06;(IPC1-7):G11C16/02 主分类号 G11C17/00
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