发明名称 |
METHOD AND DEVICE FOR ERRRO CHECK OF FIELD PROGRTAMMABLE GATE ARRAY |
摘要 |
PURPOSE:To provide an error checking method/device which can easily check whether the data written in a working field programmable gate array are normal or not. CONSTITUTION:A read control circuit 5 receives a check start signal from a processor 3 and stops the system clock transmitted to a gate array 1. Then the circuit 5 reads the data and the original data out of the array 1 and a storage 2 respectively. The bit of the data A read out of the array 1 is cleared by a status bit clear circuit 6 and then inputted to a deciding circuit 7 to which the read data B is inputted from the storage 2. The circuit 7 decides the coincidence between both data A and B. Then the circuit 7 outputs an alarm signal when no coincidence is decided between both data and sends a normal signal to the circuit 5 when the coincidence is secured between both data respectively. When the coincidence is confirmed among all data, the circuit 5 decides that the data given from the array 1 are normal starts the system clock. |
申请公布号 |
JPH05327477(A) |
申请公布日期 |
1993.12.10 |
申请号 |
JP19920133865 |
申请日期 |
1992.05.26 |
申请人 |
FUJI FACOM CORP;FUJI ELECTRIC CO LTD |
发明人 |
SASAKI ATSUSHI |
分类号 |
G01R31/317;G06F11/10;G06F11/22;H03K19/173 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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