发明名称 LAND PATTERN FOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To provide a land pattern for an integrated circuit of high quality in which an open malfunction of soldering to be effectively mounted electrically and in strength on a printed board of the circuit does not occur. CONSTITUTION:A structure in which a slit 9 formed along a direction perpendicular to the direction of leads 11 is formed is provided at the center of a land pattern 8 to be fixed with leads of an integrated circuit 10 in a land pattern 8 for mounting the circuit 10 on a printed board 7. A sufficient amount of solder 12 remains between the pattern 8 and the leads 11 by dividing its flow at the slit 9 to rigidly fix the both.</p>
申请公布号 JPH05327197(A) 申请公布日期 1993.12.10
申请号 JP19920158712 申请日期 1992.05.25
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MORIGUCHI SHIROU
分类号 H01L23/50;H05K1/11;H05K3/34;(IPC1-7):H05K3/34 主分类号 H01L23/50
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