发明名称 |
CONTROL SIGNAL GENERATING CIRCUIT FOR CLOCK RECOVERY |
摘要 |
<p>PURPOSE:To hardly generate pattern jitter and to extract a phase error output for stable clock recovery even when an amplitude of an eye pattern is fluctuated. CONSTITUTION:A phase error detection circuit 104 obtains a phase error output by obtaining a difference of input samples to shift before and after in a time axis direction. An amplitude discrimination circuit 105 discriminates whether or not the input sample exceeds a reference level. A zero crossing discrimination circuit 106 discriminates whether or not the input samples to shift before and after in the time axis direction are zero crossed. An effective phase error extracting circuit 1000 introduces a phase error signal at that time to be effective when the input sample is zero crossed and also exceeds a reference level, and employs the signal as a clock phase control signal for a clock generating circuit.</p> |
申请公布号 |
JPH05327681(A) |
申请公布日期 |
1993.12.10 |
申请号 |
JP19920126041 |
申请日期 |
1992.05.19 |
申请人 |
TOSHIBA CORP;TOSHIBA AVE CORP |
发明人 |
KOMATSU SUSUMU;ISHIKAWA TATSUYA;TAGA NOBORU |
分类号 |
H04L7/027;(IPC1-7):H04L7/027 |
主分类号 |
H04L7/027 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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