发明名称 CPFSK MODULATING/DEMODULATING CIRCUIT
摘要 PURPOSE:To hold a mark rate equal to 1/2 against any pattern train by encoding by an mBnB code. CONSTITUTION:Even an electric input signal of any mark rate inputted to an input terminal 9 is converted to an mBnB code whose mark rate is 1/2 by an mBnB encoding circuit 1. Subsequently, a signal is sent to a laser diode 3 through a laser diode driving circuit 2, modulated to CPFSK, and an optical output signal is obtained from an output terminal 10. An optical input signal inputted to an input terminal 11 is subjected to heterodyne detection by a front end circuit 4 and converted to an IF electric signal. Thereafter, its signal is amplified by an IF amplifying circuit 5, delayed and detected by a modulating circuit, and returned to a base band signal. Moreover, its signal is discriminated and reproduced by a discriminating circuit 7. Subsequently, it is converted to a binary code signal by an mBnB decoding circuit 8, and an electric output signal is obtained from an output terminal 12.
申请公布号 JPH05327797(A) 申请公布日期 1993.12.10
申请号 JP19920126556 申请日期 1992.05.20
申请人 NEC CORP 发明人 FUJINOBE YASUHIRO
分类号 H04B10/516;H01S5/068;H04B10/556;H04B10/61;H04L25/49;H04L27/12;H04L27/14 主分类号 H04B10/516
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