RESPONSE RESOLVER FOR ASSOCIATIVE MEMORIES AND PARALLEL PROCESSORS

摘要

A logic circuit for a content-addressable-memory or parallel-processor array cell implements both prioritizing and counting functions for response resolution. It includes a means for receiving from a prior cell a response-resolution token and a means for receiving the positive or negative response of the current cell to a pattern to be matched. It also includes a means for deriving as a function of the prior cell's response-resolution token a response-resolution token for the current cell that implements prioritization and counting response-resolution functions for positive or negative pattern-matching responses of the current cell. Finally, it includes a means for selecting for the current cell the appropriate response-resolution token based on the cell's positive or negative pattern-matching response and a means for sending that response-resolution token to a subsequent cell. In a preferred embodiment of the invention, the means for selecting the current cell's response-resolution token for a positive or negative pattern-matching response uses a simple pass-transistor switching circuit.