发明名称 ADAPTIVE MEMORY CONTROLLER
摘要 The operating mode of a memory controller for a random access memory having multiplexed address lines is selected to provide the highest operating speed for the addresses being presented to the memory. Each address supplied to the memory includes a row address and a column address. A page fault detector detects a page fault when the row address changes on successive transfers to the memory and detects a non-page fault when the row address remains the same on successive transfers to the memory. The operating mode is automatically selected in response to the difference between the number of page faults and the number of non-page faults to provide the highest operating speed. When the difference between the number of page faults and the number of non-page faults is equal to or greater than an upper threshold value, the memory mode is set to non-page mode. When the difference between the number of page faults and the number of non-page faults is equal to or less than a lower threshold value, the memory mode is set to page mode.
申请公布号 WO9324885(A1) 申请公布日期 1993.12.09
申请号 WO1993US05102 申请日期 1993.05.28
申请人 CABLETRON SYSTEMS, INC. 发明人 PARKER, THOMAS, B.
分类号 G06F12/02;(IPC1-7):G06F12/02 主分类号 G06F12/02
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