| 摘要 |
<p>An improved solid state storage device (SSD) with memory organized into a plurality of groups, each group including a plurality of ranks, and each rank having at least two banks sharing a bidirectional data bus. A matrix reorder circuit is used to distribute data across individual memory components in a way that prevents multi-bit uncorrectable or undetectable errors due to the failure of a single memory component. The matrix reorder circuit is used for both reading and writing data, and operates on a stream of pipelined data of arbitrary length. According to another aspect of this invention, a flaw map and additional hot spare memory are used to electrically replace failing memory components in the banks. According to another aspect of this invention, memory in a bank is accessed during one half of a reference cycle and refreshed during the second half of the reference cycle, each bank being 180 degrees out of phase with the other so that a read or write is performed on one bank while a memory refresh is performed on the other bank.</p> |
