Monitoring data transmission between processor and peripheral - has parity bits combined with address word that are stored and compared in exclusive OR logic with next incoming value

摘要

The watch dog method involves combining the transmitted address with stored address, parity code values to generate an address parity word for comparison with the next transmitted value. The address parity word generator in an interface unit has a register (1) with memory cells (10-17). Exclusive-OR gates (20-27) connect with the register memory cells. A register (31) and an adder stage (32) handle the CPU cycle and chip select (CS) signals. The register is operated by a synchronous reset (SYM RSI) and system clock (CLK). The address parity word from the register is fed back to the exclusive OR inputs for comparison with the incoming value (APAR0-APAR7). USE/ADVANTAGE - Improved reliability or error identification.