Clock recovery and synchronisation in digital data communication - establishing midpoint of input pulse from sampling at higher frequency using memory and free-running counter

摘要

The input signals are sampled and a signal is extracted which denotes the beginning of a pulse after correction (BOIC). A value between one-quarter and one-half of the inter-pulse interval (IDI) is memorised while a free-running counter is reset to 1 and begins to count up again. The input signal period is added to the content of the memory which is compared with the free-running count to determine the midpoint (ICF) for bit clock synchronisation. USE/ADVANTAGE - With either co-directional or contra-directional interfaces, simple change of function is possible with greater number of selectable data rates.