| 摘要 |
<p>A highly integrated low-power neuron computer chip which is of practical performance level and with a small power consumption can be realized. The synapse coupling can be made by a small number of elements, and the synapse weighting value with a high precision can be altered. A MOS semiconductor device has a plurality of first input gate electrodes capacitively coupled to a floating gate electrode through a second insulating film; a first MOS transistor the source electrode of which is connected to one of the first input gate electrodes; a second floating gate electrode which is provided in the first MOS transistor and is in a potentially floating state; a third floating gate electrically connected to the extension of the second floating gate electrode through a connecting part; and a tunnel junction for charging and discharging the third floating gate electrode part. The resistance of the connecting part has a value greater than at least the operating resistance of the tunnel junction.</p> |
