发明名称 CLOCK CIRCUIT
摘要 PURPOSE:To provide a clock circuit capable of automatically judging a set position and setting up a delay variable corresponding to the set position. CONSTITUTION:The clock circuit is provided with a decoding means 12 for detecting a prescribed pattern at the time of being inserted into a slot 11 having the pattern and recognizing a slot position, a multi-stage delay means 14 for inputting a clock signal inputted from a clock supplying source 13 and forming delay clock signals of plural kinds in each delay time difference generated between respective slots from the clock signal and a clock selecting means 15 for inputting respective delay clock signals outputted from respective stages of the means 14 and selecting and outputting a delay clock signal corresponding to the slot position recognized by the decoding means 12.
申请公布号 JPH05324120(A) 申请公布日期 1993.12.07
申请号 JP19920126310 申请日期 1992.05.19
申请人 PFU LTD 发明人 TSUCHIYA KENICHI
分类号 G06F1/10;H03K5/13;H03K5/133;H03L7/00 主分类号 G06F1/10
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