发明名称 EXPECTED VALUE COLLATION CIRCUIT FOR HARDWARE SIMULATOR
摘要 PURPOSE:To easily analyze the cause of a discrepancy by making the combination section of the discrepancy of the result of collation between a simulation result and an expected value clear by using signal intensity information as the attribute of the logical value of a signal. CONSTITUTION:When the signal value of a signal sin 101 are 0 or 1, it is collated with switch signals (a), (b), and (c) generated by a switch generator 16 and when the signal value is signal intensity Z, it is collated with switch signals (d), (e), and (f) generated by a switch generator 17, so that a collation result to which the signal intensity is added is outputted as rout 103. This rout 103 is not merely a coincidence/discrepancy collation result, but the output value to which the signal intensity is added, so the combination section of sine and ein is known in case of the discrepancy.
申请公布号 JPH05324753(A) 申请公布日期 1993.12.07
申请号 JP19920079677 申请日期 1992.04.01
申请人 NEC CORP;NEC MIYAGI LTD 发明人 SAITO SHOICHI;SATO TETSUYA
分类号 G01R31/28;G06F11/22;G06F17/50;G06F19/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址