| 摘要 |
PURPOSE:To accelerate speed for reading and writing data by connecting a memory part to the side of a data correcting means just before a switching means changes from a data holding state to a normal operating state, correcting data, writing them again and afterwards connecting the memory part to the side of an external terminal. CONSTITUTION:A memory circuit 1 is provided with a memory cell array 2, correction/rewrite circuit 3 to read data in the memory cell array 2 just before the change from the data holding state to the normal operating state based on a control signal S from an external system monitor circuit and to write the data again after correcting them, and switching circuit 4 to connect a bus B from the memory cell array 2 from the side of a main body or the side of a correction/rewrite circuit 3 based on the control signal S. In this case, when the bus B is connected to the side of the correction/rewrite circuit 3 by the switching circuit 4, the data are read from the memory cell array 2 for each data group. Further, after the data are corrected at an ECC 5, they are written in the memory cell array 2 again. |
