发明名称 |
Bias circuitry for content addressable memory cells of a floating gate nonvolatile memory |
摘要 |
A low power bias voltage generation circuitry for content addressable memory cells for a nonvolatile memory is described. The bias circuitry is comprised of a source follower pair and two cascaded high impedance voltage dividers. The source follower pair acts as a positive feedback loop coupling between the two high impedance voltage dividers for relatively quickly charging and settling the output node to a predetermined voltage level. The first high impedance voltage divider can relatively quickly provide an input signal to trigger the small-input-load second high impedance voltage divider. The second high impedance voltage divider comprised of two high impedance diode stacks allows most current drawing from the power supply to drive a relatively large output loading during switching. Both first and second high impedance voltage dividers help keep the DC current of the circuit to a relatively low level which helps to reduce the total power consumption of the circuit.
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申请公布号 |
US5267213(A) |
申请公布日期 |
1993.11.30 |
申请号 |
US19920861093 |
申请日期 |
1992.03.31 |
申请人 |
INTEL CORPORATION |
发明人 |
SUNG, CHIH-TA;JEX, JERRY G.;BAKER, ALAN E. |
分类号 |
G11C5/14;G11C15/04;G11C16/30;(IPC1-7):G11C13/00 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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