发明名称 Semiconductor integrated circuit with functional test mode to random access memory unit
摘要 A semiconductor integrated circuit comprises a random access memory subjected to a functional test by a testing unit with a multi-bit testing data, and the multi-bit testing data is distributed to parts of a write-in data port of the random access memory device through a plurality sets of auxiliary write-in data line groups, because the write-in data port can accept a multi-bit write-in data larger in number than the multi-bit testing data, wherein a comparator is coupled to parts of the read-out data port for producing a reporting signal indicative of consistency or inconsistency so that the testing unit examines the random access memory device with the read-out bit at one of the parts of the read-out data port and the reporting signal.
申请公布号 US5267206(A) 申请公布日期 1993.11.30
申请号 US19910718548 申请日期 1991.06.20
申请人 NEC CORPORATION 发明人 KOYABU, KUNIHIRO
分类号 G11C29/00;G01R31/28;G11C11/401;G11C29/02;G11C29/34;G11C29/48;G11C29/56;(IPC1-7):G11C7/00 主分类号 G11C29/00
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