发明名称 |
Digital processing vertical synchronization system for a television receiver set |
摘要 |
A digital vertical synchronization system for use in a television receiver is disclosed. A vertical synchronization separator circuit receives a composite synchronizing signal and separates a vertical synchronizing signal from the composite signal. A clock counter receives a clock input signal having a frequency equal to a positive integer N times as high as the frequency of a horizontal synchronizing signal separated from the composite signal. The clock counter produces a first output signal having a repetition frequency substantially equal to the vertical synchronizing signal and having a pulse width required for generating a vertical deflection signal and a second output signal having a pulse width equal to or smaller than the pulse width of the vertical synchronizing signal. A phase comparator compares the phases of the second output signal of the clock counter and the vertical synchronizing signal and produces a reset signal when the phases of the two signals are not coincident. The reset signal is applied to the reset terminal of the clock counter.
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申请公布号 |
US4227214(A) |
申请公布日期 |
1980.10.07 |
申请号 |
US19780924318 |
申请日期 |
1978.07.13 |
申请人 |
NIPPON ELECTRIC CO., LTD. |
发明人 |
MORITO, HIROSHI;YAMASHITA, KENJI |
分类号 |
H04N5/06;H04N5/12;(IPC1-7):H04N5/04;H04N5/10 |
主分类号 |
H04N5/06 |
代理机构 |
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代理人 |
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地址 |
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