| 摘要 |
A new method to produce a contact or via opening and filled metallurgy for integrated circuits. An insulating layer structure is formed over semiconductor device structures. A resist mask with substantially vertical sided openings is formed in the mask over the insulating layer and above the device elements to be electrically contacted. These device elements can be, for example source/drain regions in the semiconductor substrate, a metallurgy layer interconnecting other device element and the like. The exposed insulating layer is isotropically etched to a depth of between about 500 to 850 Angstroms to form a break in the vertical sided opening under construction. The exposed insulating layer is anisotropically etched to complete the construction of the substantially vertical sided openings through the insulating layer to a device element to be electrically contacted. A metal layer is sputter deposited over the exposed surfaces including the device elements at the bottom of the vertical sided openings, while substantially not depositing the metal upon the vertical sides of the openings. The resist mask and the metal thereover is removed by etching with the break being the attacking point of the resist etching fluid. A next level metallurgy is deposited over the exposed surfaces including the metal remaining in the vertical sided openings to form the next metallurgy level and to complete contact.
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