| 摘要 |
PURPOSE:To attain a circuit capable of simultaneously generating positive and negative input signals having pulse width independent of that of a clock input signal and preventing the appearance of a large transient current spike. CONSTITUTION:The circuit includes a clock means 52 for forming three kinds of signals whose delay and polarity are different from that of a clock input signal, the 1st output circuit having a pull-up transistor(TR) 72, and a pull-down TR 78, the 1st logical gate circuit 64 for controlling the TRs 72, 78 of the 1st output circuit in accordance with the clock signal and three kinds of signals, the 2nd output circuit having a pull-up TR 74 and a pull-down TR 82, and the 2nd logical gate circuit 84, 86, 88 for controlling the TRs of the 2nd output circuit in accordance with the clock signal and three kinds of signals. |
