| 摘要 |
<p>PURPOSE:To reduce a chip area by reducing circuit scale and to lower cost. CONSTITUTION:An A/D conversion part 1 is formed with a DELTASIGMA modulator 4, one decimation filter 5 and bus buffer 6, and a D/A conversion part 3 is formed with a bus buffer 19, one interpolation filter 20 and DELTASIGMA modulator 21. A digital signal processing part 2 connected to these parts is provided with an address control part 8, bus buffer input/output control part 7 equipped with program ROM 10 and 11 for the decimation filter and the interpolation filter, parallel multiplier 15, accumulator 14, data bus 12 and instruction bus 17. At the time of A/D conversion, the two stages of decimation are performed by the decimation filter 5, parallel multiplier 15 and accumulator 14 and at the time of D/A conversion, the two stages of interpolation are performed by the parallel multiplier 15, accumulator 14 and interpolation filter 20.</p> |
