发明名称 BUS INTERFACE CONTROL SYSTEM
摘要 <p>PURPOSE:To prevent dead lock when access is concentrated concerning the bus interface control system for a CPU in a multiprocessor system. CONSTITUTION:A bus interface control circuit 4 to connect a local bus 3 and a system bus 1 is provided with a transmission buffer 5, reception fubber 6, local bus control circuit 7 and system bus control circuit 8. The local bus control circuit 7 exchanges a start command, answer command and data between the local bus 3, transmission buffer 5 and reception buffer 6. The system bus control circuit 8 writes the start command and answer command from the system bus 1 to the reception buffer 6 and transfers the start command and answer command from the transmission buffer 5 to the system bus 1. In this case, the dead lock at the time of concentrating the access to the specified CPU is prevented by the reception control function of the answer command and the passing control function of the answer command.</p>
申请公布号 JPH05314061(A) 申请公布日期 1993.11.26
申请号 JP19920104113 申请日期 1992.04.23
申请人 FUJITSU LTD 发明人 OKAZAKI MAKOTO;SHIBATA YUJI;ASAI MASAO
分类号 G06F13/36;G06F15/16;G06F15/17;G06F15/177;(IPC1-7):G06F13/36 主分类号 G06F13/36
代理机构 代理人
主权项
地址
您可能感兴趣的专利