| 摘要 |
PURPOSE:To reduce the transmission delay of a control signal by providing a temporary register in a block secured at the side of a register file to fetch the write data with a bypass instruction and writing the data into a register file. CONSTITUTION:A register file 1 provided with (n) pieces of ports which can be read or written independently of each other is provided with a temporary register 2 which fetches the write data from a bus. In a normal read mode, the data on the register number designated by a read port are read out by a selection signal via a gate circuit 30 which switches the high and low impedances. Meanwhile the data on the register 2 are read out via a gate circuit 31 selected by a bypass instruction given from the outside. These data are written to the main body of the file 1. Thus, the number of logic stages of a peripheral circuit can be decreased and the transmission delay of a control signal can be reduced when the bypass is required. |
