| 摘要 |
PURPOSE:To reduce a steady phase difference in a locked state by adjusting the weighting rate of a leading phase pulse to a lagging phase pulse in accordance with the duty of an output clock signal. CONSTITUTION:A control part 11 changes the voltage value of a voltage signal VA by four steps by changing the value of current setting data DV by four steps and changes a reverse current Idn appearing on a current (i) impressed to a low pass filter circuit when a lagging phase pulse PD is impressed to a loop filter circuit 2. Thus the leading edge of an input signal DI is allowed to coincide with the timing of a half of an interval between the leading edges of an output clock signal CK by detecting the upper limit value and lower limit value of the current Idn in which an output clock signal CK is synchronized with the input signal DI and setting the value of the current Idn to an intermediate value between the upper and lower limits. |
