| 摘要 |
PURPOSE:To achieve the simplification and the compact configuration for an apparatus without external signal lines and input terminals by detecting the generation of an input signal having the combination which cannot be formed in ordinary operation with a signal identifying circuit, and generating a signal for simulation. CONSTITUTION:When the fact that both a read signal (a) and a write signal (b) are at a level 0 is identified with a NOR gate (signal identifying circuit) 2, a gate 2 generates the detected signal at a level 1. At this time, when a reset signal (c) as a negative logic input is at a level 0, the control signal for simulation, i.e., an output B, which is outputted from an inverter 3 and a NAND gate 4, becomes the signal at a level 1. The output signal B is used when a clock forming circuit is made to reset is simulation. Meanwhile, when both read and write signals are at a level 0, a D-type flip-flop (a second control-signal generating circuit for simulation) 1 is reset when a reset signal is made to rise up from a level 0 to 1. An output C of the flip-flop 1 is held at a level 1 and outputted. |
