| 摘要 |
A digital signal phase adjustment circuit adjusts the phase of a data signal in relation to a first local clock signal having a frequency of f. Also provided is a second local clock signal with a frequency of Nf, where N is a positive integer greater than 1. An N-bit shift register (120), clocked by the second local clock signal, generates N phase signals that are enabled in rotating sequential order during non-overlapping time intervals. One of the N phase signals is selected by a multiplexer (130) and used as the enable control signal for a data sampling circuit that is clocked by the second local clock signal. The data sampling circuit samples and outputs the data signal only when the selected phase signal is enabled, thereby outputting the data signal with a selected phase relative to the first clock signal. |
