The switching circuit comprises; CPU (41) receiving the input/ output switching command via the main processor system bus; dual port RAM (43) communicating with MPMA (3) and CPU (41); RAM (45) storing temporary data; SCC (46) controlling the input/output device; port switching control circuit (48) issusing the control signal to the interrupt handler (47).
申请公布号
KR930011203(B1)
申请公布日期
1993.11.25
申请号
KR19900022888
申请日期
1990.12.31
申请人
KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE;KOREA TELECOMMUNICATIONS CORP.
