| 摘要 |
An integrated stack of layers (22) incorporating a plurality of IC chip layers (26) has an end layer (30) which is formed of dielectric material (or covered with such material). The outer surface (42) of the end layer (30) provides a substantial area for the spaced location of a multiplicity of lead-out terminals (50), to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal (50) on the outer surface (42) of the end layer (30) is connected to IC circuitry embedded in the stack by means of conducting material in a hole (48) through the end layer (30), and a conductor (trace) (44) on the inner surface (40) of the end layer (30) which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metallization on the access plane face of the stack (22). |
