| 摘要 |
PURPOSE:To prevent generation of alarm due to a momentary phase error by providing the 2nd phase comparator circuit generating two logic levels in response to the phase difference between an output signal of a jitter generating circuit and a reference input signal and a signal interruption detecting circuit detecting the intermission of the output signal of the comparator circuit. CONSTITUTION:When a steady phase error of a phase synchronizing oscillator is a predetermined jitter amplitude or below, an output signal f3 of the 2nd phase comparator circuit 5 is a clock signal, and when a steady-state phase error exceeding jitter amplitude is generated, the signal is fixed to a logic level of '0' or '1'. Thus, the output signal f3 of the phase comparator circuit 5 is regarded as a clock signal and supervised by the signal interruption detecting circuit, then whether or not the steady- phase error of the phase synchronizing oscillator exceeds the threshold value decided by the jitter amplitude is detected easily. Further, the momentary phase abnormality such as phase sudden change of a reference input signal is canceled in a short time decided by the transient response characteristic of the phase synchronizing oscillator and the steady-state phase error is restored. Thus, a minute and accurate steady-state phase error is detected easily and the detection threshold value is decided to a duration time of the steady-state error abnormality. |
