System and method for tolerating dynamic circuit decay

摘要

A system tolerates the decay of a dynamic logic circuit (12) by preserving the logic state of the output (18) before the decay. A slow clock detector (22) detects a slow clock condition of the clock (14) fire-charging the dynamic logic circuit (12), and a tolerant storage device (24) preserves the data output (18) by command (26) of the slow clock detector (22) upon a detection of the slow clock condition. With the data thus stored, the dynamic logic circuit may be tested at a slow clock, or DC, clock-rate.