| 摘要 |
The invention relates to a filter structure operable at a filter clock frequency f, consisting of m digital decimation filters (DF1 ... DFj ... DFm), connected in parallel on the input side, which contain a multiplexer (MUX1) operable at the filter clock frequency and m pipeline filters (PF11 ... PF1m) in running at frequency f/m and which can be connected on the output side cyclically in series via a demultiplexer running at the filter clock frequency f to the filter output (Y). An m-fold throughput rate with m-fold circuit design compared with prior art transverse filters is attainable. The advantage of the invention is especially that the maximum throughput rate is determined only by the maximum processing speed of the multiplexer circuits in the decimation filters and the demultiplexer circuit, and this can also advantageously be done off-chip, e.g. using speed-optimised bipolar technology, so that the speed potential of the other filter components which, for example, use CMOS technology can be almost infinitely multiplied. |
