| 摘要 |
PCT No. PCT/JP90/00767 Sec. 371 Date Feb. 14, 1991 Sec. 102(e) Date Feb. 14, 1991 PCT Filed Jun. 13, 1990 PCT Pub. No. WO90/15999 PCT Pub. Date Dec. 27, 1990.The present invention is directed to a test pattern generator which generates test patterns for testing semiconductor integrated circuits. A DRAM is employed as a test pattern memory. A control circuit generates an address generating clock, a readout control signal, a refresh control signal and a write clock. An address generating circuit responds to the address generating clock to generate an address for reading out of the DRAM of the test pattern generator. Based on the address and the readout control signal, test patterns are read out from the DRAM of the test pattern generator and then they are written into a FiFo memory by the write clock. On the other hand, test patterns are continuously read out from the FiFo memory in synchronization with a pattern generating clock. The average readout rate from the DRAM, including the refresh period, is selected to be higher than the readout rate from the FiFo memory. When filled with the test patterns, the FiFo memory outputs a full flag signal and the control circuit responds to the full flag signal to stop the generation of the address generating clock, the readout control signal and the write clock and, when the full flag signal is reset, resumes their generation. Hence, even if the DRAM is refreshed at regular time intervals, test patterns can be continuously read out from the FiFo memory. |
