发明名称 (A) ;TRANSISTOR STRUCTURE USED AS ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To adjust the phase difference of a two-phase output from the 2nd stage frequency division circuit by connecting the 1st stage and 2nd stage frequency division circuits in cascade so as to frequency-divide sequentially a trigger signal by 1/2 and also controlling variably the threshold voltage of the 2nd stage frequency division circuit. CONSTITUTION:The 2-stage frequency division circuits 11, 12 are provided to the trigger signal S11, which is frequency-divided by 1/2 so as to obtain two-phase output signals S13, S14. Thus, a master FF circuit and a slave FF circuit 14 of the 2nd stage frequency division circuit 12 are triggered so as to be triggered by one period with the leading or trailing of a trigger signal S12 being a frequency- division output of the 1st stage frequency division circuit 11. The phase difference of the 2-phase output signals S13 and S14 is brought surely into 90 deg. even if the duty ratio of the trigger signal is not always 50% and the threshold voltage of the FF circuits 13, 14 of the frequency division circuit 12 is made adjustable, allowing to adjust the phase difference of the 2-phase output signals S13 and S14 to 90 deg. with high accuracy.
申请公布号 JPH0582794(B2) 申请公布日期 1993.11.22
申请号 JP19830148242 申请日期 1983.08.13
申请人 SONY CORP 发明人 ONGA MAKOTO
分类号 H04N9/45;H03K23/50;H04N9/455;(IPC1-7):H04N9/45 主分类号 H04N9/45
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