| 摘要 |
PURPOSE:To make variable the frequency demultiplied output of the dynamic frequency divider, by controlling the output delay of the inverter circuit. CONSTITUTION:P channel transistors Tr12-16 and N channel transistors Tr17- 21 form respectively P and N pairs to constitute the five stages of inverter circuit. Since the output of each pair is delayed by semiperiod 0.5 T0 of clock phiO up to the trailing and leading of the input 27, the period is 2.5 TO. Further, from the leading to trailing of the input 27, the period is 1.5 TO, the period of signal is 4 TO to form 1/4 frequency dividing waveform. Vc is normally at H level, but this is tentatively made to L level. Tr22 is made effective and the period from the leading of the input 27 to the trailing of the output 30 is extended from 0.5 TO- 1.5 TO, and the frequency dividing output period can be made greater by TO, that is, by one period of the clock phiO. Thus, the variable frequency division can be realized for the dynamic frequency divider. |
