| 摘要 |
PURPOSE:To systematically confirm the abnormality detecting function of a data bus extending over a long period, and further, to confirm the abnormality detecting function of the data bus even after the alteration of system configuration as well. CONSTITUTION:When a special instruction is executed by a CPU 1, an identifier ID to show a module to cause parity abnormality and data to show its timing are set to a register 61 and a counter 62 in a parity generation control part 6 respectively. When the counter 62 counts the portion of the set data, a select signal SELi (i=1 to 3) addressed to the module shown by the ID is made active by a decoder 63, and the reverse code of a normal parity code generated from a parity code generating part PGi in that module on the basis of the transferred data is attached to the same data as the parity code, and is outputted to a system bus 4. Accordingly, when a parity checker 5 detects the parity abnormality from the data on the bus and the parity code, it is confirmed that the data bus abnormality detecting function is normal. |
