| 摘要 |
<p>PURPOSE:To accelerate a processing speed without enlarging a transistor size by constituting a NAND type dynamic decoder at every group dividing an input line and connecting them in series each other. CONSTITUTION:In an address decoder 10, the address signal AD of 12 bits is divided to low-order bit side 6 bits and high-order bit side 6 bits. Then this circuit is constituted so that the NAND type dynamic decoder is formed at every group and they are connected in series each other. Then the number of an N type transistor connected to the input terminal of an inverter 15 are reduced by half except each transistor whose one end for precharging is grounded. Thus, the encoding circuit is processed at high speed without enlarging each transistor size.</p> |
