| 摘要 |
<p>PURPOSE:To prevent the delay of a rising speed in the part of a row line close to an N type MOS transistor supplying potential to the selected row line in a row decoder selecting the row line in a semiconductor memory. CONSTITUTION:This decoder is used for the row line being the common gate electrode of a memory element. For instance, a P type MOS transistor P1L is provided between the row decoder constituted of a NAND NA1L and an inverter INV1L and the row line containing points W1L, W1c, W1R. The P type MOS transistor P1R is provided between the row decoder constituted of the NAND NA1R and the inverter INV1R and the row line containing the points W1L, W1c, W1R. By the P type MOS transistors P1L, P1R, the potential is supplied to the row line when the row line is selected.</p> |
