| 摘要 |
PURPOSE:To curtail a circuit scale by realizing absolute value making processing and half-adjust processing through the use of one adder of (n-m+1)-bits at the time when the complement data of '2' of n-bits is made into an absolute value and is processed by the half-adjust processing. CONSTITUTION:A first detection circuit 9 which outputs the detection signal of logical '1' when the logic of all the data of the data 7 is '1' and in addition, the logic of the data (Xn) 3 of an (n+l)-th bit is '1', or when the logic of the data 8 is '1', the adder 12 to add the detection signal 10 to the data (Xn, Xp-1,...Xm) constituted of the data (Xn) 3 of the (n+1)-th bit and the data 11, and a second data output circuit 14 which limits the data by the data (Xn) 3 of the (n+1)-th bit when the adder 12 overflows and outputs the data as it is when it does not overflow are provided. Namely, the absolute value making processing and the half-adjust processing are realized by one adder 12 of the (n-m)-bits at the time when the absolute value making processing and the half-adjust processing of the complement data of '2' of (n+1)-bits are executed simultaneously. |
