| 摘要 |
PURPOSE:To reduce power consumption by shortening lock-up time at the time of supplying a power source and changing a frequency in a PLL frequency synthesizer circuit. CONSTITUTION:When frequency dividing number data is tranferred to a frequency dividing data holding circuit 9 or when an unlocked detecting signal ULD is outputted from an unlock detecting circuit 10, a pre-set pulse PPE which is synchronized with a frequency dividing output fR is generated from a synchronization pulse generating circuit 12 whenever a timer output PT is outputted at a specified interval from a timer circuit 11 which counts the frequency dividing output fR and pre-setting is operated in a variable frequency divider circuit 5. |
