| 摘要 |
PURPOSE:To perform arithmetic and read its result out in a single bus cycle and to shorten the execution time of the arithmetic operation by providing an arithmetic unit which uses an address bus for input data transfer and outputs the arithmetic result to a data bus. CONSTITUTION:The processor system having a processor 50 connected to the address bus and data bus and a storage device which has its address specified with data on the address bus and outputs its stored data is equipped with the arithmetic unit 51 which uses the address bus for data transfer and outputs the arithmetic result to the data bus. The input data to the arithmetic unit 51 are transferred by using the address bus, so when the data are inputted to the arithmetic unit 51, the data bus is not used. Therefore, the output data can be outputted to the data bus in a single bus cycle and the execution time of the arithmetic operation can be shortened. The arithmetic unit 51 performs the arithmetic operation according to operation codes and operand addresses inputted to an instruction register 52 through the address bus. |
