| 摘要 |
An apparatus for massive computation in integrated circuits provides the ability to calculate multiple dot products between an image focused on the integrated circuit surface and many reference patterns built into the integrated circuit, and then give an output indication for all those reference patterns where the dot product exceeds a threshold. The implementation, using current mirrors for multiplication with fixed constants, permits the integrated circuit to achieve large amounts of computation per unit area. This apparatus permits a large input data bandwidth, and by virtue of having enough computation capacity to complete a processing task on one chip, the output bandwidth is greatly reduced as well. The apparatus is employed, as an example, in a neural network. A set of connections between nodes that modify the value of the signal passed from one node to the next. Often many connections impinge on a node, and the summation of values at the node is further modified by a nonlinear function such as a threshold and amplitude limiter. Values at the input nodes represent the signals to be evaluated by the network, and values at the outputs represent an evaluation by the network of the input signals. For instance, the input could be image pixels and the outputs could represent possible patterns to which the image could be assigned. The connections between weights are often determined and modified by training data, but they can also be prespecified in total or in part based on other information about the task of the network.
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