发明名称 Decoder circuit with bypass circuitry and reduced input capacitance for greater speed
摘要 An address detection circuit is described having a node A which is precharged to the voltage of a power supply and then discharged down to ground by a strobe signal if an address match occurs. An address match is detected when a nonconventional CMOS inverter which has its input connected to node A has its output go HIGH. The nonconventional CMOS inverter utilizes a device ratio between its P-mos transistor and its N-mos transistor of approximately 10 to 1 for a 1 micron CMOS process. Prior to the strobe signal discharging the node A to ground, the output of the nonconventional inverter is held to ground by a transistor which is switched OFF when the strobe signal discharging the node A to ground is initiated.
申请公布号 US5262687(A) 申请公布日期 1993.11.16
申请号 US19920848257 申请日期 1992.03.09
申请人 ZILOG, INC. 发明人 BENHAMIDA, BOUBEKEUR
分类号 G11C8/10;H03K19/096;(IPC1-7):H03K19/20 主分类号 G11C8/10
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