| 摘要 |
The disclosed invention is a method of determining one or more parameters associated with the hierarchical circuit design. The method comprises the step of: (a) constructing a data structure representing the hierarchical circuit design; (b) synthesizing a list of attributes associated with each block in the design, the synthesis starting at the lowest level nonleaf blocks in the hierarchy and proceeding through all higher level blocks in the design; and (c) based upon the list of attributes determining in the step (b), analyzing the data structure and determining the parameter. One of the parameters determined is the delay associated with each leaf component.
|
