发明名称 |
Method of reducing waiting time jitter |
摘要 |
A method of recovering an original digital signal, after pulse stuffing, with reduced waiting time jitter. The original digital signal is written into a first elastic memory in a synchronizer. A pulse stuffed output of the synchronizer is transmitted to a desynchronizer where bits of the original signal are written into second elastic memory. Average values of fill levels of elastic memories in a synchronizer and in a desynchronizer are determined. The average value determined in the synchronizer is transmitted to the desynchronizer where a comparison of the respective average values is made in a comparator. A clock signal generating circuit in a phase locked loop is controlled by an output signal of the comparator so as to generate a clock signal. The signal bits written into the second elastic memory are read out of the second elastic memory at the rate of the generated clock signal.
|
申请公布号 |
US5263057(A) |
申请公布日期 |
1993.11.16 |
申请号 |
US19910697999 |
申请日期 |
1991.05.09 |
申请人 |
ANT NACHRICHTENTECHNIK GMBH |
发明人 |
NAWROCKI, RAINER;BRUENLE, SIEGFRIED;EHRLICH, WOLFGANG |
分类号 |
H04J3/07;(IPC1-7):H04L7/027 |
主分类号 |
H04J3/07 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|