| 摘要 |
<p>PURPOSE:To suppress the increase of a pattern area as much as possible. CONSTITUTION:A decoding circuit is provided with first signal generating circuits 2 and 4 which level-shift the values of respective bit signals in an address signal and generate the respective bit signals and the inversion signals of the respective bit signals which are level-shifted based on the respective level-shifted bit signals and a second signal generating circuit 6 which generates a selecting signal selecting the cell of a storage device 8, which is corresponding to the address signal, based on the output of the first signal generating circuit. Thus, n-level shift circuit elements are sufficient in the decoding circuit at the time of n-address bits.</p> |
