发明名称 SYNCHRONIZING DEFECT DETECTING CIRCUIT
摘要 <p>PURPOSE:To provide the synchronizing defect detecting circuit with little detection error capable of being used in common for a digital multiplex line different in transmission speed with respect to the synchronizing defect detecting circuit for the digital multiplex line in a digital line device. CONSTITUTION:This circuit is provided with a frame identification signal preparing means 1 to output a frame identification signal by counting basic clocks, abnormal frame detecting means 2 to output an abnormal frame detecting signal when the number of bits at a logical level '0' is smaller than a fixed number in one frame of a digital line, abnormal frame number counting means 3 to output a synchronizing abnormality detecting signal when the abnormal frame number detecting signals are inputted continuously as many as the fixed number of frames, synchronizing defect judging means 4 to output a synchronizing defect detecting signal while inputting synchronizing monitor information when any synchronizing abnormality detecting signal is inputted while the synchronizing monitor information detects no synchronizing, and synchronizing defect detecting condition setting means 5 to set conditions required for synchronizing defect detection by inputting signals for identifying the kinds of digital lines.</p>
申请公布号 JPH05300115(A) 申请公布日期 1993.11.12
申请号 JP19910075445 申请日期 1991.04.09
申请人 FUJITSU LTD;FUJITSU NAGOYA TSUSHIN SYST KK 发明人 MATOBA TAKENOBU
分类号 G06F11/30;G06F13/00;H04J3/06;H04J3/14;H04L7/00;(IPC1-7):H04J3/06 主分类号 G06F11/30
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