发明名称 MONOLITHIC POWER MOS INTEGRATED CIRCUIT
摘要 PURPOSE:To improve a reliability in the control operation of an outside load by canceling the adverse influence of a gate source short-circuit. CONSTITUTION:This circuit is equipped with a high power MOSFET part 20 having plural cell FET 1a-1n whose gate areas receive on/off control voltages VGa-VGn, with which a drain area D and a source area S are commonly connected, driving voltage generating circuit 18 having a cell FET driving circuit 2 which generates a control voltage VG, and sensor circuits 3, 4, and 5, and gate current detecting and interrupting part 19 having gate current detecting and interrupting circuits 11a-11n is inserted between the cell FET driving circuit 2 and each gate of the cell FET 1a-1n so that the supply of the control voltages VGa-VGn to the gates of the cell FET 1a-1n can be interrupted at the time of the generation of the gate source short-circuit at any cell FET 1a-1n.
申请公布号 JPH05299991(A) 申请公布日期 1993.11.12
申请号 JP19920124794 申请日期 1992.05.18
申请人 NEC CORP 发明人 KOISHIKAWA YUKIMASA
分类号 H03K17/08;H03K17/0812;H03K17/12 主分类号 H03K17/08
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