Logic circuit with four outputs for asynchronous switching - has four complementary FETs serving as precharging as well as charging and evaluation transistors for edge- or state-controlled operation

摘要

The input lines (I) are connected in a split-transistor-switch logic arrangement to separate n-channel and p-channel blocks (NL,PL), whose outputs (ON1,ON2,OP1,OP2) are applied selectively in pairs to a conventional evaluation circuit (AS). The gates of their respective precharging FETs (3,2) are addressed together directly by a request input (REQ) without inversion. The two additional outputs (ON2,OP2) are taken from the junctions of the respective logic blocks and their charging transistors (4,1) whose bases are also driven jointly by the request signal. ADVANTAGE - Substantial interference immunity is maintained with min. circuit complexity suited to either edge-controlled or state-controlled asynchronous logic.